10,901 research outputs found

    Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators

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    © Springer International Publishing Switzerland 2016.As the threat of fault susceptibility caused by mechanisms including variation and degradation increases, engineers must give growing consideration to error detection and correction. While the use of common fault tolerance strategies frequently causes the incursion of significant overheads in area, performance and/or power consumption, options exist that buck these trends. In particular, algorithm-based fault tolerance embodies a proven family of low-overhead error mitigation techniques able to be built upon to create self-verifying circuitry. In this paper, we present our research into the application of algorithm-based fault tolerance (ABFT) in FPGA-implemented accelerators at reduced levels of precision. This allows for the introduction of a previously unexplored tradeoff: sacrificing the observability of faults associated with low-magnitude errors for gains in area, performance and efficiency by reducing the bit-widths of logic used for error detection. We describe the implementation of a novel checksum truncation technique, analysing its effects upon overheads and allowed error. Our findings include that bit-width reduction of ABFT circuitry within a fault-tolerant accelerator used for multiplying pairs of 32 × 32 matrices resulted in the reduction of incurred area overhead by 16.7% and recovery of 8.27% of timing model fmax. These came at the cost of introducing average and maximum absolute output errors of 0.430% and 0.927%, respectively, of the maximum absolute output value under transient fault injection

    KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs

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    In a modern FPGA system-on-chip design, it is often insufficient to simply assess the total power consumption of the entire circuit by design-time estimation or runtime power rail measurement. Instead, to make better runtime decisions, it is desirable to understand the power consumed by each individual module in the system. In this work, we combine boardlevel power measurements with register-level activity counting to build an online model that produces a breakdown of power consumption within the design. Online model refinement avoids the need for a time-consuming characterisation stage and also allows the model to track long-term changes to operating conditions. Our flow is named KAPow, a (loose) acronym for ‘K’ounting Activity for Power estimation, which we show to be accurate, with per-module power estimates as close to ±5mW of true measurements, and to have low overheads. We also demonstrate an application example in which a permodule power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by over 8%

    Sustainable product development strategies: Business planning and performance implications

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    Copyright © 2012 by Institution of Mechanical Engineers. This is the author's accepted manuscript. The final published article is available from the link below.Manufacturing firms are under many financial and competitive pressures which focus attention on the performance of their manufacturing processes. In this paper the opportunities for improving the environmental impact of products within the constraints of existing manufacturing infrastructure are examined. Approaches which support sustainability in two aspects are proposed, firstly, the provision of products to the users in ways which extend the product life and secondly, manufacturing approaches which reduce resource usage. This paper outlines three different sustainable development strategies for different product types and describes the cost implications for manufacturers across the life-cycle. The performance measures affected by these strategies are examined drawing on product development case studies from a number of high technology sectors to highlight the different approaches taken. The results are intended to aid manufacturers during the earliest stages of business planning to consider alternative product development approaches which are more sustainable

    Slam excitation scales for a large wave piercing catamaran and the effect on structural response

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    A unique slamming process is observed on high speed wave piercing catamarans (WPCs) such as those manufactured by INCAT Tasmania (shown in Fig. 1). For conventional catamarans, wet-deck slamming constitutes a significant design load and is managed through proper design of the tunnel height for the proposed operating conditions. While methods have been developed for prediction of wet-deck slam occurrence and slam magnitude in conventional catamarans (for example Ge et al., 2005) the significant differences in geometry limit application to wave piercing catamarans. Although slamming of wave piercing catamarans may be categorised as a wet-deck slam, the INCAT Tasmania wave piercing catamarans include a forward centre bow to prevent deck diving which significantly alters the water entry and slamming characteristics

    Effect of Slam Force Duration on the Vibratory Response of a Lightweight High-Speed Wave-Piercing Catamaran

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    When the surface of a ship meets the water surface at an acute angle with a high relative velocity, significant short-duration forces can act on the hull plating. Such an event is referred to as a slam. Slam loads imparted on ships are generally considered to be of an impulsive nature. As such, slam loads induce vibration in the global hull structure that has implications for both hull girder bending strength and fatigue life of a vessel. A modal method is often used for structural analysis whereby higher order modes are neglected to reduce computational effort. The effect of the slam load temporal distribution on the whipping response and vertical bending moment are investigated here by using a continuous beam model with application to a 112 m INCAT wave-piercing catamaran and correlation to full-scale and model-scale experimental data. Experimental studies have indicated that the vertical bending moment is dominated by the fundamental longitudinal bending mode of the structure. However, it is shown here that although the fundamental mode is dominant in the global structural response, the higher order modes play a significant role in the early stages of the response and may not be readily identifiable if measurements are not taken sufficiently close to the slam location. A relationship between the slam duration and the relative modal response magnitudes is found, which is useful in determining the appropriate truncation of a modal solution

    architect: Arbitrary-precision Constant-hardware Iterative Compute

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    Many algorithms feature an iterative loop that converges to the result of interest. The numerical operations in such algorithms are generally implemented using finite-precision arithmetic, either fixed or floating point, most of which operate least-significant digit first. This results in a fundamental problem: if, after some time, the result has not converged, is this because we have not run the algorithm for enough iterations or because the arithmetic in some iterations was insufficiently precise? There is no easy way to answer this question, so users will often over-budget precision in the hope that the answer will always be to run for a few more iterations. We propose a fundamentally new approach: armed with the appropriate arithmetic able to generate results from most-significant digit first, we show that fixed compute-area hardware can be used to calculate an arbitrary number of algorithmic iterations to arbitrary precision, with both precision and iteration index increasing in lockstep. Thus, datapaths constructed following our principles demonstrate efficiency over their traditional arithmetic equivalents where the latter’s precisions are either under- or over-budgeted for the computation of a result to a particular accuracy. For the execution of 100 iterations of the Jacobi method, we obtain a 1.60x increase in frequency and 15.7x LUT and 50.2x flip-flop reductions over a 2048-bit parallel-in, serial-out traditional arithmetic equivalent, along with 46.2x LUT and 83.3x flip-flop decreases versus the state-of-the-art online arithmetic implementation

    Self-Excited Threshold Poisson Autoregression

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    This article studies theory and inference of an observation-driven model for time series of counts. It is assumed that the observations follow a Poisson distribution conditioned on an accompanying intensity process, which is equipped with a two-regime structure according to the magnitude of the lagged observations. Generalized from the Poisson autoregression, it allows more flexible, and even negative correlation, in the observations, which cannot be produced by the single-regime model. Classical Markov chain theory and Lyapunov’s method are used to derive the conditions under which the process has a unique invariant probability measure and to show a strong law of large numbers of the intensity process. Moreover, the asymptotic theory of the maximum likelihood estimates of the parameters is established. A simulation study and a real-data application are considered, where the model is applied to the number of major earthquakes in the world. Supplementary materials for this article are available online.postprin

    KAPow: high-accuracy, low-overhead online per-module power estimation for FPGA designs

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    In an FPGA system-on-chip design, it is often insufficient to merely assess the power consumption of the entire circuit by compile-time estimation or runtime power measurement. Instead, to make better decisions, one must understand the power consumed by each module in the system. In this work, we combine measurements of register-level switching activity and system-level power to build an adaptive online model that produces live breakdowns of power consumption within the design. Online model refinement avoids time-consuming characterisation while also allowing the model to track long-term operating condition changes. Central to our method is an automated flow that selects signals predicted to be indicative of high power consumption, instrumenting them for monitoring. We named this technique KAPow, for 'K'ounting Activity for Power estimation, which we show to be accurate and to have low overheads across a range of representative benchmarks. We also propose a strategy allowing for the identification and subsequent elimination of counters found to be of low significance at runtime, reducing algorithmic complexity without sacrificing significant accuracy. Finally, we demonstrate an application example in which a module-level power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by up to 7%

    Cosmic strings from pseudo-anomalous Fayet-Iliopoulos U(1) in D3/D7 brane inflation

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    We examine the consequences of recent developments on Fayet-Iliopoulos (FI) terms for D-term inflationary models. There is currently no known way to couple constant FI terms to supergravity consistently; only field-dependent FI terms are allowed. These are natural in string theory and we argue that the FI term in D3/D7 inflation turns out to be of this type, corresponding to a pseudo-anomalous U(1). T he anomaly is canceled by the Green-Schwarz mechanism in 4 dimensions. Inflation proceeds as usual, except that the scale is set by the GS parameter. Cosmic strings resulting from a pseudo-anomalous U(1) have potentially interesting characteristics. Originally expected to be global, they turn out to be local in the string theory context and can support currents. We outline the nature of these strings, discuss bounds on their formation, and summarize resulting cosmological consequences.Comment: 10 pages; minor changes to match published versio
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